FN3353 Rev 0.00

Page 10 of 10

December 1992

CD40105BMS

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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

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modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

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Chip Dimensions and Pad Layout

FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS

SI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

DIR

MR

SO

DOR

SI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

DIR

MR

SO

DOR

SI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

DIR

MR

SO

DOR

SI

D0

D1

D2

D3

Q0

Q1

Q2

Q3

DIR

MR

SO

DOR

SHIFT

IN

DATA OUT

READY

8 BIT

DATA

8 BIT

DATA

SHIFT

OUT

DATA IN

READY

*MASTER

RESET

*Pulse must be applied for cascading by 16 N bits.

Dimensions in parenthesis are in millimeters and are derived from the basic

inch dimensions as indicated. Grid graduations are in mils (10-3 inch).

METALLIZATION: Thickness: 11k

Å 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6k

Å, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches