BLUENRG-332VC datasheet(18/67 Pages) STMICROELECTRONICS

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Priorities among requests from channels of DMA are software programmable (four levels consisting of very

high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, and so on)

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Independent source and destination transfer size (byte, half word, word), emulating packing and

unpacking. Source/destination addresses must be aligned on the data size

•

Support for circular buffer management

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Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error) logically ORed

together in a single interrupt request for each channel

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Memory-to-memory transfer (RAM only)

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Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers

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Access to SRAMs, APB0 and APB1 peripherals as source and destination

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Programmable number of data to be transferred: up to 65536

2.14

Nested vectored interrupt controller (NVIC)

The interrupts are handled by the Cortex-M0+ nested vector interrupt controller (NVIC). NVIC controls specific

Cortex-M0+ interrupts as well as the BlueNRG-LPS peripheral interrupts.

The NVIC benefits are the following:

•

Nested vectored interrupt controller that is an integral part of the ARM Cortex-M0+

•

Tightly coupled interrupt controller provides low interrupt latency

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Control system exceptions and peripheral interrupts

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NVIC supports 32 vectored interrupts

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Four programmable interrupt priority levels with hardware priority level masking

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Software interrupt generation using the ARM exceptions SVCall and PendSV

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Support for NMI

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ARM Cortex M0+ vector table offset register VTOR implemented

NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.

2.15

Analog digital converter (ADC)

The BlueNRG-LPS embeds a 12-bit ADC. The ADC consists of a 12-bit successive approximation analog-to-

digital converter (SAR) with 2 x 8 multiplexed channels allowing measurements of up to eight external sources

and up to two internal sources.

The ADC main features are:

•

Conversion frequency is up to 1 Msps

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Three input voltage ranges are supported (0 - 1.2 V, 0 - 2.4 V, 0 - 3.6 V)

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Up to eight analog single-ended channels or four analog differential inputs or a mix of both

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Temperature sensor conversion

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Battery level conversion up to 3.6 V

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ADC continuous or single mode conversion is possible

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ADC down-sampler for multi-purpose applications to improve analog performance while off-loading the

CPU (ratio adjustable from 1 to 128)

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A watchdog feature to inform when data is outside thresholds

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DMA capability

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Interrupt sources with flags.

2.15.1

Temperature sensor

The temperature sensor (TS) generates a voltage that varies linearly with temperature. The temperature sensor

is internally connected to the ADC input channel, which is used to convert the sensor output voltage into a digital

value.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by

ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in

read-only mode.

BlueNRG-LPS

Nested vectored interrupt controller (NVIC)

DS13819 - Rev 4

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