ALED7709 datasheet(21/63 Pages) STMICROELECTRONICS

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7.7.1

Fixed-frequency current-mode controller main blocks

7.7.1.1

DAC_VOUT_CTRL

This block is a 7-bit digital to analog converter whose main purpose is to provide the voltage reference to the

converter block for optimizing VOUT.

From this block are derived also three thresholds for specific actions:

•

output overvoltage: if this threshold is reached on the VFB pin, a fault is generated and the converter is

switched OFF (VVFB,OVPT = 1.18 V)

•

skip mode: for VFB pin voltage slightly higher than VVFB,SKIP = 1.09 V, the converter enters in skip mode to

avoid reaching the overvoltage protection threshold

•

open fault: it is the value to be reached on VFB pin before getting an open channel fault recognition

(VVFB,OD = 1.03 V)

In normal operational mode, the 7-bit addresses 128 voltage steps, the minimum voltage step is 2.244 mV

granting a range of 285 mV between the VDAC,min of 0.795 V to the VDAC,max of 1.08 V.

Table 10. Converter reference voltages

VDAC,max [V]

VDAC,min [V]

VVFB,OD [V]

VVFB,SKIP [V]

VVFB,OVPT [V]

1.08

0.795

1.03

1.09

1.18

7.7.1.2

Error amplifier and COMP pin

The error amplifier is a transconductance amplifier, with a typical Gain of 600 µS, that generates a current

proportional to the error between DC-DC converter voltage reference (VDAC output) and feedback voltage (VVFB)

on the VFB pin.

If the error amplifier tries to drive the COMP pin below 0.725 V, a SKIP signal is asserted to stop switching activity

preventing the output voltage to diverge.

To avoid the COMP pin voltage going above its maximum limit of 1.9 V, a sink current clamp is present.

The reference value of this clamp is gradually increased during the soft-start, allowing a progressive current

control.

The stability of this block is granted only if a resistor in series to a compensation capacitor is connected on the

COMP pin.

7.7.1.3

COMP_2_IPROG and peak current comparator

This block is the core of the DC-DC converter control since it is responsible for controlling the peak current flowing

into the coil and, as a consequence, controlling the output power.

The COMP_2_IPROG block manages the voltage VIN-VCSNS = RSNS*IL.

The COMP pin voltage is buffered with a typical gain of 0.29167 and then it is modulated by SLOPE

compensation and compared to the voltage drop on RSNS, which is directly proportional to the coil current IL.

The above-described voltages are the inputs of the peak current comparator that is the sub-block used to turn

OFF the converter PWM cycle-by-cycle.

The peak current comparator is very fast and sensitive because input voltage could be of few tenths of mV.

There are a couple of thresholds, 200 mV and 240 mV, to have a better circuit protection.

These two thresholds are used for cycle-by-cycle current limitation and for overcurrent protection, the latter

causes a fault and then opening the external PMOS, if present.

7.7.1.4

Slope compensator

The constant frequency, peak current-mode topology has the advantage of very easy loop compensation with

output ceramic caps (reduced cost and size of the application), and fast transient response. In addition, the

intrinsic peak current measurement simplifies the current limit protection, avoiding undesired saturation of the

inductor. However, this topology has a drawback: there is inherent open loop instability when operating with a

duty-cycle greater than 0.5. This phenomenon is known as “sub-harmonic instability” and can be avoided by

adding an external ramp to the one coming from the sensed current. This compensating technique, based on the

additional ramp, is called “slope compensation”.

ALED7709

DC-DC converter controller section and output voltage optimization

DS14214 - Rev 1

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