AT25SF321B datasheet(13/63 Pages) RENESAS

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DS-AT25SF321B-179 Rev. F

Page 13

2022-06-03

AT25SF321B Datasheet

Device Operation

The AT25SF321B is controlled by a set of commands sent from a host controller, SPI Master. The SPI Master

communicates with the AT25SF321B through the SPI bus, which consists of four pins: Chip Select (CS), Serial

Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3). The AT25SF321B supports the

two most common modes, SPI modes 0 and 3. For these modes, data is latched in on the rising edge of SCK and

output on the falling edge of SCK.

Figure 4. SPI Mode 0 and 3

5.1

Dual Output Read (1-1-2)

The AT25SF321B features a Dual-Output Read mode that allows two bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, both the SI and SO pins are used as outputs for the transfer

of data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

5.2

Dual I/O Read (1-2-2)

The AT25SF321B supports Dual I/O (1-2-2) transfers, which enhance throughput over the standard SPI mode.

This mode transfers the command on the SI pin, but the address and data are transferred on the SI and SO pins.

This means that only half the number of clocks are required to transfer the address and data.

5.3

Quad Output Read (1-1-4)

The AT25SF321B features a Quad-Output Read mode that allows four bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, the SI, SO, WP, and HOLD pins are used as outputs for the

transfer of data bytes. With the Quad-Output Read Array command, the SI, WP, and HOLD pins become outputs

along with the SO pin.

5.4

Quad I/O Read (1-4-4)

The AT25SF321B supports Quad I/O (1-4-4) transfers, which enhance throughput over the standard SPI mode.

This mode transfers the command on the SI pin, but the address and data are transferred on the SI, SO, WP, and

HOLD pins. This means that only a quarter of the number of clocks are required to transfer the address and data.

With the Quad I/O Read Array command, the SI, WP, and HOLD and SO pins become inputs during the address

transfer, and switch to outputs during the data transfer.

MSB

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