AT25PE80 datasheet(2/61 Pages) RENESAS

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AT25PE80

DS-25PE80-141D–2/2022

Description

The AT25PE80 is a 1.7V minimum, serial-interface sequential access Flash memory ideally suited for a wide variety of

digital voice, image, program code, and data storage applications. The AT25PE80 also supports the RapidS serial

interface for applications requiring very high speed operation. Its 8,650,752 bits of memory are organized as 4,096 pages

of 256 bytes or 264 bytes each. In addition to the main memory, the AT25PE80 also contains two SRAM buffers of

256/264 bytes each. The buffers allow receiving of data while a page in the main memory is being reprogrammed.

Interleaving between both buffers can dramatically increase a system's ability to write a continuous data stream. In

addition, the SRAM buffers can be used as additional system scratch pad memory, and E2PROM emulation (bit or byte

alterability) can be easily handled with a self-contained three step read-modify-write operation.

Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the

DataFlash®-Lite uses a serial interface to sequentially access its data. The simple sequential access dramatically

reduces active pin count, facilitates simplified hardware layout, increases system reliability, minimizes switching noise,

and reduces package size. The device is optimized for use in many commercial and industrial applications where

high-density, low-pin count, low-voltage, and low-power are essential.

To allow for simple in-system re-programmability, the AT25PE80 does not require high input voltages for programming.

The device operates from a single 1.7V to 3.6V power supply for the erase and program and read operations. The

AT25PE80 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of the Serial Input

(SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

Pin Configurations and Pinouts

Figure 1-1.

Pinouts

Note:

The metal pad on the bottom of the UDFN package is not internally connected to a voltage potential.

This pad can be a “no connect” or connected to GND.

GND

Vcc

RESET

SCK

8-lead SOIC

Top View

GND

Vcc

RESET

SCK

8-pad UDFN

Top View

(through package)

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