21

AT25DF512C

DS-25DF512C–030G–02/2022

If the WP pin is asserted, then the BPL bit can only be set to a logical “1”. If an attempt is made to reset the BPL bit to a

logical “0” while the WP pin is asserted, then the Write Status Register Byte command will be ignored, and the WEL bit in

the Status Register will be reset back to the logical “0” state. In order to reset the BPL bit to a logical “0”, the WP pin must

be deasserted.

Figure 11-2. Write Status Register

11.3 Write Status Register Byte 2

The Write Status Register Byte 2 command is used to modify the RSTE. Using the Write Status Register Byte 2

command is the only way to modify the RSTE in the Status Register during normal device operation. Before the Write

Status Register Byte 2 command can be issued, the Write Enable command must have been previously issued to set the

WEL bit in the Status Register to a Logical 1.

To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and then the opcode 31h must be

clocked into the device followed by one byte of data. The one byte of data consists of three don’t-care bits, the RSTE bit

value, and four additional don’t-care bits (see Table 11-4). Any additional data bytes sent to the device will be ignored.

When the CS pin is deasserted, the RSTE bit in the Status Register will be modified, and the WEL bit in the Status

Register will be reset back to a Logical 0.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of

the RSTE bit will not change, and the WEL bit in the Status Register will be reset back to the Logical 0 state.

Table 11-3. Write Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BPL

X

X

X

X

BP0

X

X

SCK

CS

SI

SO

MSB

23

1

0

0000000

67

5

4

OPC ODE

10 11

9

814 15

13

12

1

MSB

DX

X

X

X

DX

X

STATUS REGISTER IN

HIGH-IMPEDANCE

Table 11-4. Write Status Register Byte 2 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

X

X

RSTE

X

X

X

X