PCF21XXC_FAM

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Product data sheet

Rev. 3 — 6 May 2015

6 of 25

NXP Semiconductors

PCF21xxC family

LCD drivers

7.

Functional description

An LCD segment or LED output is activated when the corresponding DATA bit is HIGH;

see Figure 7.

7.1 PCF2100C

When DATA bit 21 is HIGH, the A-latches (BP1) are loaded. With DATA bit 21 LOW, the

B-latches (BP2) are loaded. CLB pulse 23 transfers data from the shift register to the

selected latches.

7.2 PCF2111C

When DATA bit 33 is a HIGH, the A-latches (BP1) are loaded. With DATA bit 33 LOW, the

B-latches (BP2) are loaded. CLB pulse 35 transfers data from the shift register to the

selected latches.

7.3 PCF2112C

When DATA bit 33 is HIGH, the latches are loaded. CLB pulse 35 transfers data from the

shift register to the selected latches.

7.4 Bus control logic

The following tests are carried out by the bus control logic:

1. Test on leading zero

2. Test on number of DATA bits

3. Test of disturbed DLEN and DATA signals during transmission

If one of the test conditions is not fulfilled, no action follows the load condition (load pulse

with DLEN LOW) and the driver is ready to receive new data.

Fig 7.

C-bus data format