R31DS0118EU0101 Rev.1.01

Page 13

Apr 5, 2022

9QXL2000C Datasheet

Table 8. PCIe Refclk Additive Phase Jitter - Degraded Conditions

Parameter

Symbol

Conditions [1]

1. Differential input swing = 1600mV and input slew rate = 3.5V/ns.

Typical

Maximum

Industry

Limits

Unit

PCIe Gen1 (2.5 GT/s) [2][3][4][5]

2. The REFCLK jitter is measured after applying the filter functions found in PCI Express Base Specification 6.0, Revision 1.0. See the Test

Loads section of the data sheet for the exact measurement setup. The worst case results for each data rate are summarized in this table.

Equipment noise is removed from all measurements.

3. Jitter measurements shall be made with a capture of at least 100,000 clock cycles captured by a real-time oscilloscope (RTO) with a

sample rate of 20 GS/s or greater. Broadband oscilloscope noise must be minimized in the measurement. The measured PP jitter is

used (no extrapolation) for RTO measurements. Alternately, jitter measurements may be used with a Phase Noise Analyzer (PNA)

extending (flat) and integrating and folding the frequency content up to an offset from the carrier frequency of at least 200MHz (at

300MHz absolute frequency) below the Nyquist frequency. For PNA measurements for the 2.5 GT/s data rate, the RMS jitter is converted

to peak to peak jitter using a multiplication factor of 8.83. In the case where real-time oscilloscope and PNA measurements have both

been done and produce different results, the RTO result must be used.

4. SSC spurs from the fundamental and harmonics are removed up to a cutoff frequency of 2MHz taking care to minimize removal of non-

SSC content.

5. The rms sum of the source jitter and the additive jitter (arithmetic sum for PCIe Gen1) must be less than the jitter specification listed.

tjphPCIeG1-CC

Additive Phase Jitter,

Common Clocked

Architecture

692

839

86,000

fs pk-pk

PCIe Gen2 Hi-Band (5.0 GT/s)

[2][3][4][5]

tjphPCIeG2-CC

41

49

3,000

fs RMS

PCIe Gen2 Lo-Band (5.0 GT/s)

[2][3][4][5]

11

14

3,100

PCIe Gen3 (8.0 GT/s) [2][3][4][5]

tjphPCIeG3-CC

20

24

1,000

PCIe Gen4 (16.0 GT/s) [2][3][4][5][6]

6. Note that 700fs RMS is to be used in channel simulations to account for additional noise in a real system.

tjphPCIeG4-CC

20

24

500

PCIe Gen5 (32.0 GT/s) [2][3][4][5][7]

7. Note that 250fs RMS is to be used in channel simulations to account for additional noise in a real system.

tjphPCIeG5-CC

8

10

150

PCIe Gen6 (64.0 GT/s) [2][3][4][5][8]

8. Note that 150fs RMS is to be used in channel simulations to account for additional noise in a real system.

tjphPCIeG6-CC

5

6

100

PCIe Gen2 IR (5.0 GT/s) [2][3][9]

9. The PCI Express Base Specification 6.0, Revision 1.0 provides the filters necessary to calculate SRIS jitter values; it does not provide

specification limits, hence the reference to this footnote in the Limit column. SRIS values are informative only. A common practice is to

split the common clock budget in half. For 16GT/s data rates and above, the user must choose whether to use the output jitter

specification, or the input jitter specification, which includes an allocation for the jitter added by the channel. Using 32GT/s, the Refclk

jitter budget is 150fs RMS. One half of the Refclk jitter budget is 106fs RMS. At the clock input, the system must deliver 250fs RMS. One

half of this value is 177fs RMS. If the clock is placed next to the PCIe device in an SRIS system, the channel is very short and the user

may choose to use this more relaxed value as the jitter limit.

tjphPCIeG2-IR

IR (SRNS, SRIS)

Architecture

52

63

N/A

fs RMS

PCIe Gen3 IR (8.0 GT/s) [2][3][5][9]

tjphPCIeG3-IR

14

17

PCIe Gen4 IR (16.0 GT/s) [2][3][9]

tjphPCIeG4-IR

14

17

PCIe Gen5 IR (32.0 GT/s) [2][3][9]

tjphPCIeG5-IR

12

15

PCIe Gen6 IR (64.0 GT/s) [2][3][9]

tjphPCIeG6-IR

15

19