7

Typical application diagram

Figure 5. Typical application diagram – half-bridge configuration

VH_A

GNDISO_A

SD

GND

INA

INB

iLOCK

BRAKE

VH_B

GNDISO_B

BRAKE

GND_PWR

Load_ Phase

HV_BUS

VH_LS

VH_HS

HIN

LIN

SD

Cfilt

Rfilt

VDD

MCU

Cfilt

Rfilt

Cfilt

Rfilt

VDD

VDD

1uF

100nF

VDD or GND

CLAMP_B

GON_B

GOFF_B

GND_HS

1uF

100nF

GND_LS

CLAMP_A

GON_A

GOFF_A

1uF

100nF

I

S

O

L

A

T

I

O

N

Control

Logic

Floating ground B

Floating ground A

Floating

Section

Control

Logic

UVLO

VH

Level

Shifter

VCLAMPth

+

Floating

Section

Control

Logic

UVLO

VH

Level

Shifter

VCLAMPth

+

VDD

Figure 6. Typical application diagram – half-bridge configuration with negative gate driving

VH_A

GNDISO_A

SD

GND

INA

INB

iLOCK

BRAKE

VH_B

GNDISO_B

BRAKE

GND_PWR

Load_ Phase

HV_BUS

VL_HS

VL_LS

VH_LS

VH_HS

HIN

LIN

SD

Cfilt

Rfilt

VDD

MCU

Cfilt

Rfilt

Cfilt

Rfilt

VDD

VDD

1uF

100nF

VDD or GND

CLAMP_B

GON_B

GOFF_B

GND_HS

+

VL

VH

+

GND_LS

+

VL

VH

+

CLAMP_A

GON_A

GOFF_A

I

S

O

L

A

T

I

O

N

Control

Logic

Floating ground B

Floating ground A

Floating

Section

Control

Logic

UVLO

VH

Level

Shifter

VCLAMPth

+

Floating

Section

Control

Logic

UVLO

VH

Level

Shifter

VCLAMPth

+

VDD

STGAP2HD

Typical application diagram

DS13652 - Rev 2

page 13/24