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STM32U595AI датащи(PDF) 338 Page - STMicroelectronics |
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STM32U595AI датащи(HTML) 338 Page - STMicroelectronics |
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338 / 377 page ![]() Electrical characteristics STM32U59xxx 338/377 DS13633 Rev 1 5.3.42 SAI characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized inTable 32, with the following configuration: • Output speed set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling range 1 Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (SCK, SD, FS). Table 146. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK SAI main clock output -- 50 MHz fSCK SAI clock frequency(2) Master transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 26 Master transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18 Master receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 21.5 Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V - 27.5 Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V - 18 Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V - 50 tv(FS) FS valid time Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V - 16 ns Master mode 1.71 V ≤ VDDIOX ≤ 3.6 V - 23 th(FS) FS hold time Master mode 7 - tsu(FS) FS setup time Slave mode 2.5 - th(FS) FS hold time Slave mode 1 - tsu(SD_A_MR) Data input setup time Master receiver 4 - tsu(SD_B_SR) Slave receiver 3 - th(SD_A_MR) Data input hold time Master receiver 2 - th(SD_B_SR) Slave receiver 1 - tv(SD_B_ST) Data output valid time Slave transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V - 18 Slave transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V - 27.5 th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 8 - tv(SD_A_MT) Data output valid time Master transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V - 19 Master transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V - 27.5 th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 8 - |
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