STM32U595AI datasheet(58/377 Pages) STMICROELECTRONICS

58 / 377 page

Functional overview

STM32U59xxx

58/377

DS13633 Rev 1

foreground, and memory-to memory with pixel format conversion, blending and fixed

color background

•

Area filling with a fixed color

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Copy from an area to another

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Copy with pixel format conversion between source and destination images

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Copy from two sources with independent color format and blending

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Output buffer byte swapping to support refresh of displays through parallel interface

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Abort and suspend of DMA2D operations

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Watermark interrupt on a user programmable destination line

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Interrupt generation on bus error or access conflict

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Interrupt generation on process completion

3.21

Chrom-GRC (GFXMMU)

The GFXMMU is a graphical oriented memory management unit aimed to:

•

Optimize memory usage according to the display shape

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Cache linear accesses to the frame buffer

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Prefetch data

The GFXMMU main features are:

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Fully programmable display shape to physically store only the visible pixel

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Up to 4 virtual buffers

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Each virtual buffer have 3072 or 4096 bytes per line and 1024 lines

•

Each virtual buffer can be physically mapped to any system memory

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Optional cache for linear accesses

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Cache can be locked to a virtual buffer

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Cache prefetch mechanism for linear accesses anticipation

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Interrupt in case of buffer overflow (1 per buffer)

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Interrupt in case of memory transfer error

3.22

Interrupts and events

3.22.1

Nested vectored interrupt controller (NVIC)

The devices embed a NVIC that is able to manage 16 priority levels and to handle up to 138

maskable interrupt channels plus the 16 interrupt lines of the Cortex-M33.

The NVIC benefits are the following:

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closely coupled NVIC giving low-latency interrupt processing

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interrupt entry vector table address passed directly to the core

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early processing of interrupts

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processing of late arriving higher priority interrupts

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support for tail chaining

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processor state automatically saved

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