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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32U595AI датащи(PDF) 315 Page - STMicroelectronics |
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STM32U595AI датащи(HTML) 315 Page - STMicroelectronics |
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315 / 377 page  DS13633 Rev 1 315/377 STM32U59xxx Electrical characteristics 343 Synchronous waveforms and timings Figure 59 to Figure 62 represent synchronous waveforms and Table 131 to Table 134 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable • MemoryType = FMC_MemoryType_CRAM • WriteBurst = FMC_WriteBurst_Enable • CLKDivision = 1 • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period. • Maximum FMC_CLK = 80 MHz for 2.7 V ≤ VDD ≤ 3.6 V, with CL = 15pF and with CL = 20 pF • Maximum FMC_CLK = 80 MHz for 1.71 V ≤ VDD ≤ 1.9 V with CL = 15pF and with CL = 20 pF Table 130. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 8 × tHCLK - 1 8 × tHCLK + 1 ns tw(NWE) FMC_NWE low time 6 × tHCLK - 1 6 × tHCLK + 1 tsu(NWAIT_NE) FMC_NWAIT(2) valid before FMC_NEx high 5 × tHCLK + 13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4 × tHCLK + 12 - 1. Evaluated by characterization. Not tested in production. 2. NWAIT pulse is equal to one HCLK cycle. |
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