M59DR032EA datasheet(12/43 Pages) STMICROELECTRONICS

12 / 43 page

M59DR032EA, M59DR032EB

12/43

Block Erase Command. The Block Erase com-

mand can be used to erase a block. It sets all the

bits within the selected block to ’1’. All previous

data in the block is lost. If the block is protected

then the Erase operation will abort, the data in the

block will not be changed and the device will return

to Read Array mode. It is not necessary to pre-pro-

gram the block as the Program/Erase Controller

does it automatically before erasing.

Six Bus Write cycles are required to issue the

command.

The first two write cycles unlock the Command

Interface.

The third write cycles sets up the command

the fourth and fifth write cycles repeat the unlock

sequence

the sixth write cycle latches the block address

and confirms the command.

Additional Block Erase confirm cycles can be is-

sued to erase other blocks without further unlock

cycles. All blocks must belong to the same bank; if

a new block belonging to the other bank is given,

the operation is aborted.

The additional Block Erase confirm cycles must be

given within the DQ3 erase timeout period. Each

time a new confirm cycle is issued the timeout pe-

riod restarts. The status of the internal timer can

be monitored through the level of DQ3, see Status

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read.

After the command has been issued the Read/Re-

set command will be accepted during the DQ3 tim-

eout period, after that only the Erase Suspend

command will be accepted.

On successful completion of the Block Erase com-

mand, the device returns to Read Array mode.

Bank Erase Command. The Bank Erase com-

mand can be used to erase a bank. It sets all the

bits within the selected bank to ’1’. All previous

data in the bank is lost. The Bank Erase command

will ignore any protected blocks within the bank. If

all blocks in the bank are protected then the Bank

Erase operation will abort and the data in the bank

will not be changed. It is not necessary to pre-pro-

gram the bank as the Program/Erase Controller

does it automatically before erasing.

As for the Block Erase command six Bus Write cy-

cles are required to issue the command.

The first two write cycles unlock the Command

Interface.

The third write cycles sets up the command

the fourth and fifth write cycles repeat the unlock

sequence

the sixth write cycle latches the block address

and confirms the command.

Once the command is issued the device outputs

the Status Register data when any address within

the bank is read.

For optimum performance, Bank Erase com-

mands should be limited to a maximum of 100 Pro-

gram/Erase cycles per Block. After 100 Program/

Erase cycles the internal algorithm will still operate

properly but some degradation in performance

may occur.

Dual operations are not supported during Bank

Erase operations and the command cannot be

suspended.

On successful completion of the Bank Erase com-

mand, the device returns to Read Array mode.

Erase Suspend Command. The Erase Suspend

command is used to pause a Block Erase opera-

tion. In a Dual Bank memory it can be used to read

data within the bank where an Erase operation is

in progress. It is also possible to program data in

blocks not being erased.

One bus write cycle is required to issue the Erase

Suspend command. The Program/Erase Control-

ler suspends the Erase operation within 20µs of

the Erase Suspend command being issued and

bits 7, 6 and/ or 2 of the Status Register are set to

‘1’. The device is then automatically set to Read

mode. The command can be addressed to any

bank.

During Erase Suspend the memory will accept the

Erase Resume, Program, Read CFI Query, Auto

Select, Block Lock, Block Unlock and Block Lock-

Down commands.

Erase Resume Command. The Erase Resume

command can be used to restart the Program/

Erase Controller after an Erase Suspend com-

mand has paused it. One Bus Write cycle is re-

quired to issue the command. The command must

be issued to an address within the bank being

erased. The unlock cycles are not required.

Protection Register Program Command. The

Protection Register Program command is used to

Program the Protection Register (One-Time-Pro-

grammable (OTP) segment and Protection Regis-

ter Lock). The OTP segment is programmed 16

bits at a time. When shipped all bits in the segment

are set to ‘1’. The user can only program the bits

to ‘0’.

Four write cycles are required to issue the Protec-

tion Register Program command.

The first two bus cycles unlock the Command

Interface.

The third bus cycle sets up the Protection

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