82P33813 datasheet(13/70 Pages) RENESAS

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September 5, 2017

82P33813 Datasheet

Figure 4. Single Blade Architecture

3.1.2

DISTRIBUTED ARCHITECTURE FOR T-BC AND T-

TSC, IEEE 1588 IN THE TIMING CARD

Figure 5 shows a distributed architecture that can represent a Tele-

com Boundary clock (T-BC) or telecom time slave clocks (T-TSC) imple-

mentation where the IEEE 1588 is handled in the timing card. In this

architecture IEEE 1588 protocol is terminated in the timing card. The

local host processor will run the clock recovery algorithm (servo) and run

the alternate Best Master Clock Algorithm (BMCA) according to ITU-T

G.8275.1. The alternate BMCA determines which Telecom Grand Mas-

ter (T-GM) to be used as the source of time. In Figure 5, one of the

packet data port will be a slave port and the others will be master ports

of the T-BC. The first revision of G.8275.1 assumes that the frequency is

transported by synchronous Ethernet (SyncE) and the phase is con-

trolled by IEEE 1588. G.8271.1 shows a model for Telecom Boundary

Clock (T-BC) with SyncE assistance. 82P33813 has a combo mode that

allows the implementation of the T-BC and T-TSC with SyncE assis-

tance. It is very important to control the IEEE 1588 clocks independently

of the SyncE clocks. It maybe also important to be able to suppress

phase transients on the SyncE clocks to not affect the IEEE 1588 clocks.

See Chapter 3.3.2.3 for mode details on the combo mode.

ITU-T G.8273.2 has two classes of T-BC and T-TSC clocks. Class A

must meet 50ns of phase alignment inside an equipment. Class B must

meet 20ns of phase alignment inside an equipment, this will allow an

Operator to deploy longer chains of T-BCs. To be able to meet such tight

requirements, it is very important to control the delays between the tim-

ing card and the line cards. 82P33813 has individual phase adjustments

to allow very fine control of the phase of the clocks inside the equipment.

See Chapter 3.3.7.1, Chapter 3.3.7.2, and Chapter 3.3.7.3 for details on

the phase adjustment control modes.

The architecture depicted in Figure 5 can also be used for a phase

and time application using G.8275.2 and frequency application using

G.8265.1 (see Chapter 3.1.4.1). The key difference in this case is that

the T-BC, T-TSC or a packet slave clock will experience Packet Delay

Variation (PDV) due to the network that does not have IEEE 1588 full

timing support (T-BC is not deployed in every node of the network). An

algorithm to filter PDV must be implemented in this case.

Also for the architecture shown in Figure 5, there is an active timing

card and a redundant timing card. This is done in equipment that are

designed to have a redundant timing card in case of failure of the pri-

mary timing card. The redundant timing card mimics the output of the

active timing card, so in case of failure the system will still provide proper

synchronization.

Single

Blade

CDR

1588 Time

Stamp

PHY

1588 DCO

TSCK

Host Processor

(Transport layer Protocol,

IEEE 1588 protocol and

Servo)

SyncE-RxCK

SyncE-TxCK

Time stamps

Ethernet

TCXO/OCXO

1PPS

BITS/SSU

SyncE (T0)

1PPS

LOS

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