82P33741 datasheet(21/59 Pages) RENESAS

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September 15, 2017

82P33741 Datasheet

A qualified input clock with the highest priority is selected by revertive

switching. If more than one qualified input clock INn is available, then it

is important to set appropriate priorities to the input clocks, two input

clocks must not have the same priority.

In Non-Revertive switching, the DPLL1/2 selected input clock is not

switched when another qualified input clock with a higher priority than

the current selected input clock becomes available. In this case, the

selected input clock is switched and a qualified input clock with the high-

est priority is selected only when the DPLL1/2 selected input clock is dis-

qualified. If more than one qualified input clock INn is available, then it is

important to set appropriate priorities to the input clocks, two input

clocks must not have the same priority.

3.1.3.3.3 Selected / Qualified Input Clocks Indication

The selected input clock is indicated by the CURRENTLY_SELECT-

ED_INPUT[3:0] bits.

When the device is configured in Automatic selection and Revertive

switching is enabled, the input clock indicated by the CURRENTLY_SE-

LECTED_INPUT[3:0] bits is the same as the one indicated by the HIGH-

EST_PRIORITY_VALIDATED[3:0] bits.

3.1.3.3.4 Input Clock Loss of Signal

There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify

the input clock. If they are set high, then the associated input clock is

disqualified to be used as an input clock, and therefore the DPLLs will

not lock to that particular input clock.

The 4 LOS pins can be associated with any input clock by setting bits

LOS_EN in INn_LOS_SYNC_CNFG (1<n<14) register. By default, the

LOS pins are not associated with any input.

3.1.4

DPLL LOCKING PROCESS

The following events are always monitored for the DPLLs locking

process:

• Fast Loss;

• Fine Phase Loss;

• Hard Limit Exceeding.

For proper operation, COARSE_PH_LOS_LIMT_EN must be set to

3.1.4.1

Fast Loss

A fast loss is triggered when the selected input clock misses 3 con-

secutive clock cycles. It is cleared once an active clock edge is detected.

For all DPLL1 and DPLL2 the occurrence of the fast loss will result in

the DPLL to unlock if the FAST_LOS_SW bit is ‘1’. For DPLL3, the

occurrence of the fast loss will result in the DPLL to unlock regardless of

the FAST_LOS_SW bit.

3.1.4.2

Fine Phase Loss

The DPLL compares the selected input clock with the feedback sig-

nal. If the phase-compared result exceeds the fine phase limit pro-

grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is

triggered. It is cleared once the phase-compared result is within the fine

phase limit.

For

greatest

jitter

and

wander

tolerance,

set

the

PH_LOS_FINE_LIMT[2:0] to the largest value.

The occurrence of the fine phase loss will result in DPLL to unlock if

the FINE_PH_LOS_LIMT_EN bit is ‘1’.

3.1.4.3

Hard Limit Exceeding

Two limits are available for this monitoring. They are DPLL soft limit

and DPLL hard limit. When the frequency of the DPLL output with

respect to the system clock exceeds the DPLL soft / hard limit, a DPLL

soft / hard alarm will be raised; the alarm is cleared once the frequency

is within the corresponding limit. The occurrence of the DPLL soft alarm

does not affect the DPLL locking status. The DPLL soft alarm is indi-

cated by the corresponding DPLL_SOFT_FREQ_ALARM bit. The

occurrence of the DPLL hard alarm will result in the DPLL to unlock if the

FREQ_LIMT_PH_LOS bit is ‘1’.

The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits

and can be calculated as follows:

DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724

The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]

bits and can be calculated as follows:

DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014

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