VSC8541-01 datasheet(45/100 Pages) MICROSEMI

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Registers

VMDS-10496 VSC8541-01 Datasheet Revision 4.2

4.2.9

1000BASE-T Control

The 1000BASE-T functionality is controlled by the bits in register 9 of the main register space. The

following table shows the settings and readouts available.

Note: Transmitter test mode (bits 15:13) operates in the manner described in IEEE 802.3 section 40.6.1.1.2.

4.2.10

1000BASE-T Status

The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T

communications enabled in the device. The following table shows the readouts.

Table 30 •

1000BASE-T Control, Address 9 (0x09)

Bit

Name

Access Description

Default

15:13 Transmitter test mode

R/W

000: Normal.

001: Mode 1: Transmit waveform test.

010: Mode 2: Transmit jitter test as master.

011: Mode 3: Transmit jitter test as slave.

100: Mode 4: Transmitter distortion test.

101–111: Reserved.

000

Master/slave manual configuration R/W

1: Master/slave manual configuration enabled.

Master/slave value

R/W

This register is only valid when bit 9.12 is set to 1.

1: Configure PHY as master during negotiation.

0: Configure PHY as slave during negotiation.

Port type

R/W

1: Multi-port device.

0: Single-port device.

1000BASE-T FDX capability

R/W

1: PHY is 1000BASE-T FDX capable.

1000BASE-T HDX capability

R/W

1: PHY is 1000BASE-T HDX capable.

7:0

Reserved

Reserved.

Table 31 •

1000BASE-T Status, Address 10 (0x0A)

Bit Name

Access Description

Default

Master/slave configuration fault

This bit latches high; self-clearing.

1: Master/slave configuration fault detected.

0: No master/slave configuration fault

detected.

Master/slave configuration resolution RO

1: Local PHY configuration resolved to master.

0: Local PHY configuration resolved to slave.

Local receiver status

1: Local receiver is operating normally.

Remote receiver status

1: Remote receiver OK.

LP 1000BASE-T FDX capability

1: LP 1000BASE-T FDX capable.

LP 1000BASE-T HDX capability

1: LP 1000BASE-T HDX capable.

9:8 Reserved

Reserved.

7:0 Idle error count

Self-clearing register.

0x00

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