Philips Semiconductors

Product specification

74LVC841A

10-bit transparent latch with 5-volt tolerant

inputs/outputs (3-State)

1998 Jun 17

3

LOGIC SYMBOL (IEEE/IEC)

SV01724

LE

13

Q7

Q8

Q9

2

D0

Q0

19

20

21

22

23

9

10

11

D7

D8

D9

8

D6

Q6

7

D5

Q5

14

6

D4

Q4

15

5

D3

Q3

16

4

D2

Q2

17

3

D1

Q1

18

1

OE

LOGIC SYMBOL

SV01725

23

22

21

20

19

18

17

16

15

14

2

3

4

5

6

7

8

9

10

11

C1

EN

13

1

1D

LOGIC DIAGRAM

DD

D

LE

SV01726

Q

D

LE

OE

DQ

LATCH

1

LE LE

DQ

LATCH

2

LE LE

DQ

LATCH

3

LE LE

DQ

LATCH

4

LE LE

DQ

LATCH

5

LE LE

DQ

LATCH

6

LE LE

DQ

LATCH

7

LE LE

QQQ

LATCH

8

LATCH

9

LATCH

10

LE

LE

LE

LE

LE

LE

LE

LE

OPERATING MODES

INPUTS

INTERNAL

OUTPUTS

OPERATING MODES

OE

LE

LATCHES

Enable and read register (transparent mode)

L

L

H

H

L

H

L

H

L

H

Latch and read register

L

L

↓

↓

l

h

L

H

L

H

latch register and disable outputs

H

H

X

X

l

h

L

H

Z

Z

Hold

L

L

X

NC

NC

NOTES:

H

=

HIGH voltage level

h

=

HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition

L

=

LOW voltage level

l

=

LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition

X

=

don’t care

Z

=

high impedance OFF-state

NC =

no change