VLINE 500 V/DIV

ISENSE1 2 A/DIV

IINJ 10 A/DIV

VSENSE1 10 V/DIV

10 s/DIV

(a)

(b)

VLINE 500 V/DIV

ISENSE1 2 A/DIV

IINJ 10 A/DIV

VSENSE1 10 V/DIV

10 s/DIV

Figure 9-8. IEC 61000-4-5 Surge, 5-kV Repetitive Strike at 10-Second Intervals – Positive (a), Negative (b)

9.3 Power Supply Recommendations

The TPSF12C3 AEF IC operates over a wide supply voltage range of 8 V to 16 V (typically 12 V) and is

referenced to chassis ground of the system. The characteristics of this VDD bias supply must be compatible with

the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the VDD

supply must be capable of delivering the required supply current to the loaded AEF circuit.

The supply rail can already be present in the system or can be derived using a low-cost solution with an auxiliary

winding from an isolated flyback regulator. Connect a 1-µF ceramic capacitor close to the VDD and IGND pins of

the TPSF12C3. Ensure that the VDD ripple voltage is less than 50 mV peak-to-peak.

9.4 Layout

Proper PCB design and layout is important in active EMI circuits (where high regulator voltage and current slew

rates exist) to achieve reliable device operation and design robustness. Furthermore, the EMI performance of

the design depends to a large extent on PCB layout.

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze

AEF performance. Figure 9-9 and Figure 9-10 show a recommended layout for the TPSF12C3 with optimized

placement and routing of the IC and small-signal components.

• Route the sense lines S1, S2, S3 and S4 away from the INJ line. Avoid coupling between sense and inject

traces.

• Place a ceramic capacitor close to the VDD and IGND pins. Minimize the area of the loop to the VDD and

IGND pins.

• Place the compensation network copnponents close to the COMP1 and COMP2 pins. Reduce noise

sensitivity of the feedback compensation network path by placing components RG, CG1 and CG2 close to

the COMP pins. COMP2 is the inverting input to the AEF anplifier and represents a high-impedance node

sensitive to noise.

• Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal

impedance. Provide adequate heatsinking for the TPSF12C3 to keep the junction temperature below 150°C.

A top-side ground plane is an important heat-dissipating area. Use several heat-sinking vias to connect IGND

(pin 14) and REFGND (pin 9) to the PCB ground plane.

TPSF12C3

SNVSCB8 – MARCH 2023

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