9.4 Layout

9.4.1 Layout Guidelines

Because the LSF0108-Q1 is a switch-type level translator, the signal integrity is highly related with a pull-up

resistor and PCB capacitance condition.

• Short signal trace as possible to reduce capacitance and minimize stub from pull-up resistor.

• Place LSF close to high voltage side.

• Select the appropriate pull-up resistor that applies to translation levels and driving capability of transmitter.

9.4.2 Layout Example

LSF0108-Q1

1

GND

20

EN

2

Vref_A

19

Vref_B

3

A1

18

B1

4

A2

17

B2

10

A8

11

B8

Minimize Stub as possible

Short Signal Trace as possible

Figure 9-9. Short Trace Layout

Device PCB

TP1

SD Controller

(1.8 V IO)

TP2

LSF0108-Q1

SDIO level translator

SDIO Connnector

(3.3 V IO)

Figure 9-10. Device Placement

Time (ns)

0

2.5

5

7.5

10

12.5

15

17.5

20

22.5

25

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

D011

Input

Output

Figure 9-11. Waveform From TP1

(Pull-Up Resistor: 160-Ω and 50-pF Capacitance

3.3 V to 1.8 V at 100 MHz)

Time (ns)

0

3

6

9

12

15

18

21

24

27

30

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

D010

Input

Output

Figure 9-12. Waveform From TP2

(Pull-Up Resistor: 160-Ω and 50-pF Capacitance

1.8 V to 3.3 V at 100 MHz)

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LSF0108-Q1

SDLS967F – MAY 2016 – REVISED APRIL 2023

Copyright © 2023 Texas Instruments Incorporated

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Product Folder Links: LSF0108-Q1