74LVC273D datasheet(2/10 Pages) PHILIPS

2 / 10 page

Philips Semiconductors

Product specification

74LVC273

Octal D-type flip-flop with reset; positive-edge trigger

1998 May 20

853-2064 19419

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Conforms to JEDEC standard 8-1A

• Inputs accept voltages up to 5.5V

• CMOS low power consumption

• Direct interface with TTL levels

• Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74LVC273 is a low-voltage Si-gate CMOS device, superior to

most advanced CMOS compatible TTL families.

The 74LVC273 has eight edge-triggered , D-type flip-flops with

individual D inputs and Q outputs. The common clock (CP) and

master reset (MR) inputs load and reset (clear) all flip-flops

simultaneously. The state of each D input, one set-up time before

the LOW-to-HIGH clock transition, is transferred to the

corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or data inputs

by a LOW voltage level on the MR input.

The device is useful for applications where the true output only is

required and the clock and master reset are common to all storage

elements.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr =tf v2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

CP to Qn;

MR to Qn

CL = 50pF

VCC = 3.3V

6.0

Maximum clock frequency

230

MHz

fmax

Maximum clock frequency

230

MHz

Input capacitance

5.0

CPD

Power dissipation

capacitance per flip-flop

VI = GND to VCC1

NOTE:

1CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD

VCC2 x fi )S (CL

VCC2

fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL

VCC2

fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

20-Pin Plastic SO

–40

°C to +85°C

74LVC273 D

SOT163-1

20-Pin Plastic SSOP Type II

–40

°C to +85°C

74LVC273 DB

SOT339-1

20-Pin Plastic TSSOP Type I

–40

°C to +85°C

74LVC273 PW

74LVC273PW DH

SOT360-1

PIN CONFIGURATION

GND

VCC

SY00051

PIN DESCRIPTION

NUMBER

SYMBOL

FUNCTION

Master reset input (active LOW)

2, 5, 6,

9, 12, 15,

16, 19

Q0 – Q7

Flip-flop outputs

3, 4, 7,

8, 13, 14,

17, 18

D0 – D7

Data inputs

GND

Ground (0V)

Clock input (LOW-to-HIGH,

edge-triggered)

VCC

Positive power supply

74LVC273D датащи(PDF) 2 Page - NXP Semiconductors

74LVC273D датащи(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10

датащи скачать

ссылки URL