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74LVC240APW датащи(PDF) 2 Page - NXP Semiconductors

номер детали 74LVC240APW
подробное описание детали  Octal buffer/line driver with 5-volt tolerant inputs/outputs; inverting 3-State
PDF  11 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC240APW датащи(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC240A
Octal buffer/line driver with 5-volt
tolerant inputs/outputs; inverting (3-State)
2
1998 May 20
853-1981 19419
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High impedance when V
CC = 0V
DESCRIPTION
The 74LVC240A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. These features allow the use of
these devices as translators in a mixed 3.3V/5V environment.
The ‘240A is an octal non-inverting buffer/line driver with 3-State
outputs. The 3-State outputs are controlled by the output enable
inputs 1OE and 2OE. A HIGH on nOE causes the outputs to
assume a high impedance OFF-state. Schmitt-trigger action at all
inputs makes the circuit highly tolerant for slower input rise and fall
times.
The ’240’ is functionally identical to the ’244’, but the ’244’ has
inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
1An to 1Yn;
2An to 2Yn
CL = 50pF
VCC = 3.3V
3.5
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per
buffer
Notes 1 and 2
20
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic Small Outline (SO)
–40
°C to +85°C
74LVC240A D
74LVC240A D
SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II
–40
°C to +85°C
74LVC240A DB
74LVC240A DB
SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I
–40
°C to +85°C
74LVC240A PW
7LVC240APW DH
SOT360-1



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