5P1103 datasheet(6/31 Pages) RENESAS

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PROGRAMMABLE FANOUT BUFFER

R31DS0085EU0100

September 15, 2021

5P1103 DATASHEET

Example 1: The crystal load capacitance is specified as 8pF

and the stray capacitance at each crystal pin is Cs=1.5pF.

Assuming equal capacitance value at XIN and XOUT, the

equation is as follows:

8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2

→

0.5pF × XTAL[5:0] = 5.5pF

→ XTAL[5:0] = 11 (decimal)

Example 2: The crystal load capacitance is specified as 12pF

and the stray capacitance Cs is unknown. Footprints for

external capacitors Ce are added and a worst case Cs of 5pF

is used. For now we use Cs + Ce = 5pF and the right value for

Ce can be determined later to make 5pF together with Cs.

12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2

→

XTAL[5:0] = 20 (decimal)

Manual Switchover Mode

When SM[1:0] is “0x”, the redundant inputs are in manual

switchover mode. In this mode, CLKSEL pin is used to switch

between the primary and secondary clock sources. The

primary and secondary clock source setting is determined by

the PRIMSRC bit. During the switchover, no glitches will occur

at the output of the device, although there may be frequency

and phase drift, depending on the exact phase and frequency

relationship between the primary and secondary clocks.

OTP Interface

The 5P1103 can also store its configuration in an internal OTP.

The contents of the device's internal programming registers

can be saved to the OTP by setting burn_start (W114[3]) to

high and can be loaded back to the internal programming

registers by setting usr_rd_start(W114[0]) to high.

To initiate a save or restore using I2C, only two bytes are

transferred. The Device Address is issued with the read/write

bit set to “0”, followed by the appropriate command code. The

save or restore instruction executes after the STOP condition

is issued by the Master, during which time the 5P1103 will not

generate Acknowledge bits. The 5P1103 will acknowledge the

instructions after it has completed execution of them. During

that time, the I2C bus should be interpreted as busy by all

other users of the bus.

On power-up of the 5P1103, an automatic restore is

performed to load the OTP contents into the internal

programming registers. The 5P1103 will be ready to accept a

programming instruction once it acknowledges its 7-bit I2C

address.

Availability of Primary and Secondary I2C addresses to allow

programming for multiple devices in a system. The I2C slave

address can be changed from the default 0xD4 to 0xD0 by

programming the I2C_ADDR bit D0. VersaClock 5

Programming Guide provides detailed I2C programming

guidelines and register map.

SD/OE Pin Function

The polarity of the SD/OE signal pin can be programmed to be

either active HIGH or LOW with the SP bit (W16[1]). When SP

is “0” (default), the pin becomes active LOW and when SP is

“1”, the pin becomes active HIGH. The SD/OE pin can be

configured as either to shutdown the PLL or to enable/disable

the outputs. The SH bit controls the configuration of the

SD/OE pin The SH bit needs to be high for SD/OE pin to be

configured as SD.

When configured as SD, device is shut down, differential

outputs are driven High/low, and the single-ended LVCMOS

outputs are driven low. When configured as OE, and outputs

are disabled, the outputs are driven high/low.

Table 4: SD/OE Pin Function Truth Table

Output Skew

Rising edges of all outputs are automatically phase aligned.

Output Drivers

The OUT1 to OUT2 clock outputs are provided with

type in the appropriate register, any of these outputs can

support LVCMOS, LVPECL, HCSL or LVDS logic levels

The operating voltage ranges of each output is determined by

SD/OE Input

OEn

OSn

Global Shutdown

OUTn

SH bit SP bit OSn bit OEn bit SD/OE

OUTn

Tri-state2

Output active

Output driven High Low

Tri-state2

Output active

Output driven High Low

Output active

Tri-state2

Output active

Tri-state2

Output active

Output driven High Low

Output driven High Low 1

Note 1 : Global Shutdown

Note 2 : Tri-state regardless of OEn bits

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