Philips Semiconductors

Product specification

74LVC163

Presettable synchronous 4-bit binary counter;

synchronous reset

1998 May 20

8

AC WAVEFORMS

output load.

CP INPUT

Qn, TC OUTPUT

SY00071

GND

Waveform 1.

delays, the clock pulse width and the maximum clock

frequency.

CET INPUT

TC OUTPUT

GND

SY00072

Waveform 2.

Input (CET) to output (TC) propagation delays.

MR

INPUT

CP INPUT

SC0013

9

GND

GND

Waveform 3.

Master reset (MR) pulse width, the master reset

clock (CP) removal times.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

VM

GND

GND

GND

PE INPUT

CP INPUT

SC00137

Waveform 4.

parallel enable input (PE).

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

VM

VM

VM

tsu

th

tsu

th

SC00138

GND

GND

CEP, CET

INPUT

CP INPUT

Waveform 5.

CEP and CET setup and hold times.

TEST CIRCUIT

SWITCH POSITION

PULSE

GENERATOR

RT

VI

D.U.T.

VO

CL

VCC

500

Ω

Open

GND

< 2.7V

TEST

Open

2.7V

2.7–3.6V

50pF

500

Ω

SV00903

Waveform 6.

Load circuitry for switching times.