HC05V7GRSSLASHD datasheet(58/170 Pages) NXP

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HC05V7GRS/D датащи(PDF) 58 Page - NXP Semiconductors

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SECTION 6: RESETS

Page 44

MC68HC05V7 Specification Rev. 1.0

If any other reset function is active at the end of the LVR reset signal, the RST signal will

remain in the reset condition until the other reset condition(s) end.

6.2.5

ILLEGAL ADDRESS

An illegal address reset is generated when the CPU attempts to fetch an instruction from

either unimplemented address space ($01C0

to $023F and $02C0 to $17FF) or I/O

address space ($0000 to $003F).

The illegal address reset will activate the internal pulldown device connected to the RESET

pin.

6.2.6

DISABLED STOP INSTRUCTION

When the mask option is selected to disable the STOP instruction, execution of a STOP

instruction results in an internal reset.

This activates the internal pulldown device

connected to the RESET pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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