Preliminary Technical Data

AD5628/AD5648/AD5668

Rev. PrA| Page 21 of 24

Clear Code Register

The AD5628/AD5648/AD5668 gives the option of clearing any one or all DAC channels to 0, midscale or fullscale code. Command 0101

is reserved for the Clear Code function. See Table1. These clear code values are software-programmable by setting two bits (DB1 and

DB0) in the control register.

Table shows how the state of the bits corresponds to the clear code values of the device. Upon execution of the hardware /CLR pin

(active LOW), the DAC output is cleared to the clear code register value (default setting is zero). See Table 8 for contents of the Input

the part.

Clear Code Register

CR1

CR0

Clears to code

0

0

0000h

0

1

8000h

1

0

FFFFh

1

1

No operation

Table 7. Clear Code Register

MSB

LSB

DB31 –

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB2-

DB19

DB1

DB0

X

0

1

0

1

1/0

1/0

1/0

1/0

x

1/0

1/0

Don’t

Cares

COMMAND BITS (C2-C0)

ADDRESS BITS (A3 – A0)

Don’t

Cares

Clear Code

Register (CR1-

CR0)

Table 8. 32-Bit Input Shift Register Contents Clear Code Function

LDAC Function

The outputs of all DACs may be updated simultaneously using the hardware /LDAC pin.

Synchronous LDAC:

The DAC registers are updated after new data is read in on the falling edge of the 32nd SCLK pulse. LDAC can be

permanently low or pulsed as in Figure 1.

Asynchronous LDAC:

The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the

DAC registers are updated with the contents of the input register.

The outputs of all DACs may be updated simultaneously using the /LDAC function, with the added functionality of selecting through

software any number of DAC channels to synchronize.

Writing to the DAC using command 0110, the hardware /LDAC pin can be overwritten by setting the bits of the 8-bit /LDAC register

(DB7-DB0) . SeeTable 9 for the /LDAC mode of operation. The default for each channel is “0” ie /LDAC pin works normally. Setting the

bits to a “1” means the DAC channel will be updated regardless of the state of the /LDAC pin. This gives the added benefit of allowing

any combination of channels to be synchronously updated. See Table 10 for contents of the Input Shift Register during the /LDAC

overwrite mode of operation.