MCP2030-ISLASHST datasheet(4/66 Pages) MICROCHIP

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MCP2030

DS21981A-page 4

AC Characteristics

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage

2.0V

≤ VDD ≤ 3.6V

Operating temperature

-40°C

≤ TA ≤ +85°C

LCCOM connected to VSS

LC Signal Input

Sinusoidal 300 mVPP

Carrier Frequency

125 kHz

LCCOM connected to VSS

Parameters

Sym.

Min.

Typ†

Max.

Units

Conditions

Input Sensitivity

VSENSE

13.0

mVPP

VDD = 3.0V

Output enable filter disabled

AGCSIG = 0; MODMIN = 00

(33% modulation depth setting)

Input = Continuous Wave (CW)

Output = Logic level transition from

low-to-high at sensitivity level for CW input.

Coil de-Q’ing Voltage -

RF Limiter (RFLM) must be active

VDE_Q

3—

VDD = 3.0V, Force IIN = 5

μA (worst case)

RF Limiter Turn-on Resistance

(LCX, LCY, LCZ)

RFLM

—

300

700

VDD = 2.0V, VIN = 8 VDC

Sensitivity Reduction

SADJ

—

-30

—

VDD = 3.0V

No sensitivity reduction selected

Max. reduction selected

Monotonic increment in attenuation value

from setting = 0000 to 1111 by design

Minimum Modulation Depth

60% setting

33% setting

14% setting

VIN_MOD

—

VDD = 3.0V

See Section 5.21 “Minimum Modulation

Depth Requirement for Input Signal”.

See Modulation Depth Definition in

Figure 5-5.

Carrier frequency

FCARRIER

—125

—

kHz

Input modulation frequency

FMOD

—

kHz

Input data rate with NRZ data format.

VDD = 3.0V

Minimum modulation depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

LCX Tuning Capacitor

CTUNX

—

VDD = 3.0V,

Config. Reg. 1, bits <6:1> Setting = 000000

63 pF ±30%

Config. Reg. 1, bits <6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

LCY Tuning Capacitor

CTUNY

—

VDD = 3.0V,

Config. Reg. 2, bits <6:1> Setting = 000000

63 pF ±30%

Config. Reg. 2, bits <6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

LCZ Tuning Capacitor

CTUNZ

—

VDD = 3.0V,

Config. Reg. 3, bits<6:1> Setting = 000000

63 pF ±30%

Config. Reg. 3, bits<6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

Q of Internal Tuning Capacitors

Q_C

50 *

—

Demodulator Charge Time

(delay time of demodulated output to rise)

TDR

—50

—

μsV

DD = 3.0V

Minimum modulation depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

Parameter is characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note

Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).

Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF).

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