74HC75 datasheet(2/7 Pages) PHILIPS

2 / 7 page

December 1990

Philips Semiconductors

Product speciﬁcation

Quad bistable transparent latch

74HC/HCT75

FEATURES

• Complementary Q and Q outputs

• VCC and GND on the centre pins

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT75 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT75 have four bistable latches. The two

latches are simultaneously controlled by one of two active

HIGH enable inputs (LE1-2 and LE3-4). When LEn-n is

HIGH, the data enters the latches and appears at the nQ

outputs. The nQ outputs follow the data inputs (nD) as long

as LEn-n is HIGH (transparent). The data on the nD inputs

one set-up time prior to the HIGH-to-LOW transition of the

LEn-n will be stored in the latches. The latched outputs

remain stable as long as the LEn-n is LOW.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf =6ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC −1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5V

nD to nQ, nQ11

LEn-n to nQ, nQ11

input capacitance

3.5

CPD

power dissipation capacitance per latch

notes 1 and 2

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