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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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74HC595 датащи(PDF) 13 Page - NXP Semiconductors |
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74HC595 датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 28 page  2003 Jun 25 13 Philips Semiconductors Product specification 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state 74HC595; 74HCT595 AC CHARACTERISTICS Family 74HC GND = 0 V; tr =tf = 6 ns; CL =50pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb =25 °C tPHL/tPLH propagation delay SH_CP to Q7’ see Fig.7 2.0 − 52 160 ns 4.5 − 19 32 ns 6.0 − 15 27 ns propagation delay ST_CP to Qn see Fig.8 2.0 − 55 175 ns 4.5 − 20 35 ns 6.0 − 16 30 ns tPHL propagation delay MR to Q7’ see Fig.10 2.0 − 47 175 ns 4.5 − 17 35 ns 6.0 − 14 30 ns tPZH/tPZL 3-state output enable time OE to Qn see Fig.11 2.0 − 47 150 ns 4.5 − 17 30 ns 6.0 − 14 26 ns tPHZ/tPLZ 3-state output disable time OE to Qn see Fig.11 2.0 − 41 150 ns 4.5 − 15 30 ns 6.0 − 12 26 ns tW shift clock pulse width HIGH or LOW see Fig.7 2.0 75 17 − ns 4.5 15 6 − ns 6.0 13 5 − ns storage clock pulse width HIGH or LOW see Fig.8 2.0 75 11 − ns 4.5 15 4 − ns 6.0 13 3 − ns master reset pulse width LOW see Fig.10 2.0 75 17 − ns 4.5 15 6.0 − ns 6.0 13 5.0 − ns tsu set-up time DS to SH_CP see Fig.9 2.0 50 11 − ns 4.5 10 4.0 − ns 6.0 9.0 3.0 − ns set-up time SH_CP to ST_CP see Fig.8 2.0 75 22 − ns 4.5 15 8 − ns 6.0 13 7 − ns th hold time DS to SH_CP see Fig.9 2.0 +3 −6 − ns 4.5 +3 −2 − ns 6.0 +3 −2 − ns |
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