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STE2004 датащи(PDF) 60 Page - STMicroelectronics

номер детали STE2004
подробное описание детали  102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
PDF  66 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STE2004 датащи(HTML) 60 Page - STMicroelectronics

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Figure 75. Serial interface Timing
Notes: 1.
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with
an input voltage swing of VSS to VDD
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. CVLCD is the filtering CApacitor on VLCD
6. Trise and Tfall (30%-70%) -10ns
7. I2C bus AC Characteristics are tested by correlation
Table 23 Electrical Characteristics (continued)
AC OPERATION (continued)
(VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.5 V; Vss1,2 = 0V; VLCD = 4.5 to 15 V; Tamb =-40 to 85°C; unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SERIAL INTERFACE
FSCLK
Clock Frequency
VDD1 = 1.7V;
8
MHz
TCYC
Clock Cycle SCLK
125
ns
TPWH1
SCLK pulse width HIGH
60
ns
TPWL1
SCLK Pulse width LOW
60
ns
TS2
CS setup time
VDD1 = 1.7V
40
ns
TH2
CS hold time
50
ns
TPWH2
CS minimum high time
50
ns
TS3
SD/C setup time
30
ns
TH3
SD/C hold time
30
ns
TS4
SDIN setup time
30
ns
TH4
SDIN hold time
40
ns
TS5
SDOUT Access Time
30
ns
TH5
SDOUT Disable Time vs. SCLK
0
20
ns
TH6
SDOUT Disable Time vs. CS
0
20
ns
D/C
CS
tS2
tS3
tS4
tH2
tPWH2
SDIN
SCLK
tH3
tH4
tPWL1
tWH1
tS2
tCYC
SOUT
tS5
tH5
tH6
LR0096
F
frame
f
osc
960
----------
=



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