AM85C30-16JC datasheet(27/68 Pages) AMD

27 / 68 page

AMD

Am85C30

65432

FOY FDA

RR7

FIFO Data Available Status

1 = Status Reads Will Come From FIFO

0 = Status Reads Will Come From SCC

FIFO Overflow Status

1 = FIFO Overflowed During Operation

0 = Normal

RR6

Read From FIFO

LSB Byte Count

RR15

••

•

••

ENH

FEN

Status FIFO Enable Control Bit

1 = Status and Byte Count Will be

0= Status Will Not be Held (SCC Emulation Mode)

Held in the Status FIFO Until Read

= No Change From NMOS SCC DFN

•

65432

ENH: SDLC/HDLC Enhancement Status

1 = Enhancements Enabled

0 = Enhancements Disabled

Figure 15. SCC Additional Registers

10216F-19

Enable

The byte counter is enabled when the SCC is in the

SDLC/HDLC mode and WR15 bit 2 is set to 1.

Reset

The byte counter is reset whenever an SDLC flag char-

acter is received. The reset is timed so that the contents

of the byte counter are successfully written into the

FIFO.

Increment

The byte counter is incremented by writes to the data

FIFO. The counter represents the number of bytes re-

ceived by the SCC, rather than the number of bytes

transferred from the SCC. (These counts may differ by

up to the number of bytes in the receive data FIFO con-

tained in the SCC.)

Am85C30 SDLC/HDLC Enhancement

SDLC/HDLC enhancements on the Am85C30 are en-

abled or disabled via bits D2 or D0 in WR15. Bit D2 deter-

mines whether or not the 10

× 19 bit SDLC/HDLC

frame status FIFO is enabled while bit D0 determines

whether or not other enhancements are enabled via

WR7

′. Table 3 shows what functions on the Am85C30

are enabled when these bits are set.

When bit D2 of WR15 is set to 1, two additional registers

(RR6 and RR7) per channel specific to the 10

× 19 bit

Frame Status FIFO are made available. The Am85C30

Table 4.

Bit D0 of WR15 determines whether or not other en-

hancements pertinent only to SDLC/HDLC mode opera-

tion are available for programming via WR7

′ as shown

below. Write Register 7 prime (WR7

′) can be written to

when bit D0 of WR15 is set to 1. When this bit is set, writ-

ing to WR7 (flag register) actually writes to WR7

′. If bit

D6 of this register is set to 1, previously unreadable reg-

isters WR3, WR4, WR5, and WR10 are readable by the

pro-cessor. In addition, WR7

′ is also readable by having

this bit set. WR3 is read when a bogus RR9 register is

accessed during a read cycle. WR10 is read by access-

ing RR11, and WR7

′ is accessed by executing a read to

RR14. The Am85C30 register map with bit D0 of WR15

and bit D6 of WR7

′ set is shown in Table 5.

If both bits D0 and D2 of WR15 are set to 1 and D6 of

WR7

′ is set to 1, then the Am85C30 register map is as

shown in Table 6.

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