74HC4060 datasheet(2/12 Pages) PHILIPS

2 / 12 page

December 1990

Philips Semiconductors

Product speciﬁcation

14-stage binary ripple counter with oscillator

74HC/HCT4060

FEATURES

• All active components on chip

• RC or crystal oscillator configuration

• Output capability: standard (except for RTC and CTC)

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4060 are high-speed Si-gate CMOS

devices and are pin compatible with “4060” of the “4000B”

series. They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT4060 are 14-stage ripple-carry

counter/dividers and oscillators with three oscillator

terminals (RS, RTC and CTC), ten buffered outputs (Q3 to

Q9 and Q11 to Q13) and an overriding asynchronous

master reset (MR).

The oscillator configuration allows design of either RC or

crystal oscillator circuits. The oscillator may be replaced by

an external clock signal at input RS. In this case keep the

other oscillator pins (RTC and CTC) floating.

The counter advances on the negative-going transition of

RS. A HIGH level on MR resets the counter (Q3 to Q9 and

Q11 to Q13 = LOW), independent of other input conditions.

In the HCT version, the MR input is TTL compatible, but

the RS input has CMOS input switching levels and can be

driven by a TTL output by using a pull-up resistor to VCC.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

3. For formula on dynamic power dissipation see next pages.

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5 V

RS to Q3

Qn to Qn+1

66ns

tPHL

MR to Qn

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1, 2 and 3

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