74HC258DB datasheet(2/16 Pages) PHILIPS

2 / 16 page

1999 Sep 02

Philips Semiconductors

Product speciﬁcation

Quad 2-input multiplexer; 3-state; inverting

74HC/HCT258

FEATURES

• Inverting data path

• 3-state outputs interface directly with system bus

• Output capability: bus driver

• ICC category: MSI.

GENERAL DESCRIPTION

The 74HC/HCT258 are high-speed Si-gate CMOS devices

and are pin compatible with Low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT258 have four identical 2-input multiplexers

with 3-state outputs, which select 4 bits of data from two

sources and are controlled by a common data select

input (S).

The data inputs from source 0 (1I0 to 4I0) are selected

when input S is LOW and the data inputs from source 1

(1I1 to 4I1) are selected when S is HIGH.

Data appears at the outputs (1Yto4Y) in inverted form

from the select inputs.

The ‘258’ is the logic implementation of a 4-pole, 2-position

switch, where the position of the switch is determined by

the logic levels applied to S. The outputs are forced to a

high impedance OFF-state when OE is HIGH.

The logic equations for the outputs are:

The ‘258’ is identical to the ‘257’ but has inverting outputs.

()

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑ (CL × VCC2 × fo) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in Volts.

2. For HC the condition is VI = GND to VCC;

For HCT the condition is VI = GND to VCC − 1.5 V.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/tPLH

propagation delay

CL = 15 pF;

VCC =5V

nI0,nI1 to nY

StonY

1416ns

input capacitance

3.5

CPD

power dissipation capacitance per multiplexer

notes 1 and 2

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