L99DZ100G datasheet(53/197 Pages) STMICROELECTRONICS

53 / 197 page

DS11546 Rev 5

53/197

L99DZ100G, L99DZ100GP

Electrical specifications

196

Table 30. CAN transmit data input: pin TxDC

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VTXDCLOW

Input voltage dominant

level

1.0

1.45

2.0

VTXDCHIGH

Input voltage recessive

level

1.2

1.85

2.3

VTXDCHYS

VTXDCHIGH-VTXDCLOW

0.2

0.4

0.7

RTXDCPU

TXDC pull up resistor

kΩ

td,TXDC(dom-rec)

TXDC - CANH,L delay

time dominant -

recessive

RL = 60 Ω; CL = 100 pF; 70 %

VRXD – 30% VDIFF; TXDC rise

time = 10 ns (10% - 90%)(1)

0120

td,TXDC(rec-diff)

TXDC - CANH,L delay

time recessive -

dominant

RL = 60 Ω; CL = 100 pF; 30 %

VRXD – 70% VDIFF; TXDC fall

time = 10 ns (90% - 10%)(1)

0120

tdom(TXDC)

TXDC dominant time-out

0.8

1. Guaranteed by design.

Table 31. CAN receive data output: Pin RxDC

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VRXDCLOW

Output voltage dominant level IRXDC = 2 mA

0.2

0.5

VRXDCHIGH

Output voltage recessive

level

IRXDC = -2 mA

V1 - 0.5 V1 - 0.2

tr,RXDC

RXDC rise time

CL = 15 pF; 

30% - 70% VRXDC(1)

025

tf,RXDC

RXDC fall time

CL = 15 pF; 

70% - 30% VRXDC(1)

025

td,RXDC(dom-rec)

CANH,L – RXDC delay time

dominant - recessive

CL = 15 pF; 

30% VDIFF – 70% VRXDC(1)

120

td,RXDC(rec - dom)

CANH,L – RXDC delay time

recessive - dominant

CL = 15 pF; 

70% VDIFF – 30% VRXDC(1)

120

1. Guaranteed by design.

Table 32. CAN transmitter dominant output characteristics

Symbol

Parameter

Test condition

Min.

Typ.

Max. Unit

VCANHdom

Single ended CANH voltage

level in dominant state

VTXDC = VTXDCLOW; RL = 50 Ω;

65 Ω

2.75

3.5

4.5

VCANLdom

Single ended CANL voltage

level in dominant state

VTXDC = VTXDCLOW; 

RL = 50 Ω; 65 Ω

0.5

1.5

2.25

VDIFF,dom

Differential output voltage in

dominant state: VCANHdom-

VCANLdom

VTXDC = VTXDCLOW; 

RL = 50 Ω; 65 Ω

1.5

2.0

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