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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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UPSD325X датащи(PDF) 132 Page - STMicroelectronics |
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UPSD325X датащи(HTML) 132 Page - STMicroelectronics |
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132 / 176 page  µPSD325X DEVICES 132/176 Ports A and B – Functionality and Structure Ports A and B have similar functionality and struc- ture, as shown in Figure 65. The two ports can be configured to perform one or more of the following functions: s MCU I/O Mode s CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B. McellBC7- McellBC0 can be connected to Port B or Port C. s CPLD Input – Via the Input Macrocells (IMC). s Latched Address output – Provide latched address output as per Table 94. s Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode. s Peripheral Mode – Port A only (80-pin package) Figure 65. Port A and Port B Structure DATA OUT REG. DQ D G Q DQ DQ WR WR WR ADDRESS MACROCELL OUTPUTS ENABLE PRODUCT TERM (.OE) ALE READ MUX P D B CPLD - INPUT CONTROL REG. DIR REG. INPUT MACROCELL ENABLE OUT DATA IN OUTPUT SELECT OUTPUT MUX PORT A OR B PIN DATA OUT ADDRESS A[ 7:0] AI06605 |
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