1998 Jun 10

3

Philips Semiconductors

Product specification

Dual JK flip-flop with set and reset;

negative-edge trigger

74HC/HCT112

ORDERING INFORMATION

PIN DESCRIPTION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

74HC112D;

74HCT112D

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

74HC112DB;

74HCT112DB

SSOP16

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

74HC112N;

74HCT112N

DIP16

plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

74HC112PW;

74HCT112PW

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

PIN NO.

SYMBOL

NAME AND FUNCTION

1, 13

1CP, 2CP

clock input (HIGH-to-LOW, edge triggered)

2, 12

1K, 2K

data inputs; flip-flops 1 and 2

3, 11

1J, 2J

data inputs; flip-flops 1 and 2

4, 10

set inputs (active LOW)

5, 9

1Q, 2Q

true flip-flop outputs

6, 7

1Q, 2Q

complement flip-flop outputs

8

GND

ground (0 V)

15, 14

reset inputs (active LOW)

16

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.