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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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74HC03D датащи(PDF) 8 Page - NXP Semiconductors |
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74HC03D датащи(HTML) 8 Page - NXP Semiconductors |
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8 / 8 page  December 1990 8 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC/HCT03 APPLICATION INFORMATION Notes to Figs 9 and 10 If VP − VCC (R) > 0.5 V a positive current will flow into the receiver (as described in the “USER GUIDE”; input/output protection), this will not affect the receiver provided the current does not exceed 20 mA. At VCC < 4.5 V, RON (max) is not guaranteed; RON(max) can be estimated using Figs 33 and 34 in the “USER GUIDE”. Note to Application information All values given are typical unless otherwise specified. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. Fig.9 Pull-up configuration. (b) (a) (1) RON(max) = 0.26 V / 4 mA = 65 Ω (at 25 °C) Fig.10 Minimum resistive load as a function of the pull-up voltage. (1) VCC (R) = 2.0 V; VIL = 0.5 V. (2) VCC (R) = 5.0 V; VIL = 0.8 V. (3) VCC (R) = 4.5 V; VIL = 1.35 V. (4) VCC (R) = 6.0 V; VIL = 1.8 V. |
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