LM3495 datasheet(21/26 Pages) NSC

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Design Considerations (Continued)

The bandwidth of this example circuit is 49 kHz, with a phase

margin of 46˚.

Efficiency Calculations

A reasonable estimation for the efficiency,

η, of a buck

regulator controlled by the LM3495 can be obtained by

adding together the loss in each current carrying element,

TOTAL-LOSS, and using the equation:

The following shows an efficiency calculation to complement

the Typical Application circuit. Output power for this circuit is

O = 1.2V x 10A = 12W. Input voltage is assumed to be 12V,

and the calculations used assume that the converter runs in

CCM.

Chip Operating Loss

This term accounts for the current drawn at the VIN pin. This

current, I

IN, drives the logic circuitry and the power FETs.

The gate driving loss term from the power FET section of

Design Considerations is included in the chip operating loss.

For the LM3495, I

IN is equal to the steady state operating

current, I

Q, plus the FET driving current, IGC. Power is lost as

this I

IN passes through the internal linear regulator of the

LM3495.

GC =(QG-HI +QG-LO)xfOSC

GC = (11nC + 33nC) x 500 kHz = 22 mA

Q is typically 1.8 mA, taken from the Electrical Characteris-

tics table. Chip Operating Loss is then:

Q =VIN x(IQ +IGC)

Q = 12V x (1.8mA + 22mA) = 0.29W

High-Side FET Switching Loss

SW =0.5xVIN xIO x(tR +tF)xfSW

SW = 0.5 x 12V x 10A x (5 ns + 8 ns) x 500 kHz = 0.39W

FET Conduction Loss

C =D(I

O xRDSON-HI x 1.3)

C-HI = 0.1 x (100 x 0.013) = 0.13W

C =(1-D)(I

O xRDSON-LO x 1.3)

C-LO = 0.9 x (100 x 0.0044) = 0.40W

SNS Loss (if used)

SNS =(1-D)((IO)

2 xR

SNS)

Not used in this example.

Input Capacitor Loss

This term represents the loss as input ripple current passes

through the ESR of the input capacitor bank. In this equation

‘n’ is the number of capacitors in parallel.

IN = (3A)

2 x2m

Ω) = 0.018W

Output Inductor Loss

LOUT =(IO)

2 xR

LOUT = (10A)

2 x3m

Ω = 0.3W

Total Loss

LOSS = 1.53W

Efficiency

n = 12W/(12W +1.50W) = 88%

Layout Considerations

To produce an optimal power solution with the LM3495, good

layout and design of the PCB are as important as the com-

ponent selection. The following are several guidelines to aid

in creating a good layout.

KELVIN TRACES FOR SENSE LINES

The pins of the low-side FET should be connected as close

as possible to the SW/CSH and CSL pins. Each pin should

use a separate trace, and the traces should be run parallel to

each other to give common mode rejection. Although it can

be difficult in a compact design, these traces should stay

away from the output inductor if possible, to avoid coupling

stray flux.

The SNS pin should also be connected using a separate

Kelvin trace, running from the positive pin/pad of the output

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FIGURE 10. Overall Loop Gain and Phase

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