Philips Semiconductors

Product specification

74F821/822/823/824/825/826

Bus interface registers

1996 Jan 05

8

LOGIC DIAGRAM FOR 74F824

GND = Pin 12

D0

D

R

Q

Q0

2

23

D1

Q1

3

22

D2

Q2

4

21

D3

Q3

5

20

D4

Q4

6

19

D5

Q5

7

18

D6

Q6

8

17

D7

Q7

9

16

D8

Q8

10

15

11

MR

CP

CE

14

SF00503A

1

OE

13

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

FUNCTION TABLE for 74F823 and 74F824

INPUTS

OUTPUTS

INPUTS

74F823

74F824

OPERATING MODE

OE

MR

CE*

CP

Dn

Q

Q

L

L

X

X

X

L

L

Clear

L

H

L

↑

h

H

L

Load and read data

L

H

L

↑

l

L

H

Load and read data

L

H

H

X

X

NC

NC

Hold

H

X

X

X

X

Z

Z

High impedance

H = High-voltage level

h

= High state must be present one setup time before the low-to-high clock transition

L

= Low-voltage level

l

= Low state must be present one setup time before the low-to-high clock transition

NC= No change

X = Don’t care

Z = High impedance “off” state

*

= Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders

or other potentially glitch prone device on the CE input.

↑ = Low-to-high clock transition

LOGIC DIAGRAM FOR 74F825

GND = Pin 12

D0

D

R

Q

Q0

3

22

D1

Q1

4

21

D2

Q2

5

20

D3

Q3

6

19

D4

Q4

7

18

D5

Q5

8

17

D6

Q6

9

16

D7

Q7

10

15

11

MR

CP

CE

14

1

OE0

SF00504A

13

CP

23

2

OE1

OE2

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP

D

R

Q

CP