VN7000AY datasheet(47/48 Pages) STMICROELECTRONICS

47 / 48 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Configuration diagram (top view)........................................................ 4

Figure 3.

Current and voltage conventions........................................................ 5

Figure 4.

IOUT/ISENSE vs. IOUT - High RDSON mode .............................................. 13

Figure 5.

Current sense precision vs. IOUT - High RDSON mode........................................ 14

Figure 6.

IOUT/ISENSE vs. IOUT - Low RDSON mode ............................................... 14

Figure 7.

Current sense precision vs. IOUT - Low RDSON mode ........................................ 15

Figure 8.

Switching time and Pulse skew ........................................................ 15

Figure 9.

MultiSense timings (current sense mode)................................................. 16

Figure 10.

Multisense timings (chip temperature and VCC sense mode).................................... 16

Figure 11.

TDSTKON ....................................................................... 17

Figure 12.

Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ......................... 19

Figure 13.

Latch functionality - behavior in hard short circuit condition..................................... 19

Figure 14.

OFF-state output current ............................................................ 20

Figure 15.

Standby current .................................................................. 20

Figure 16.

IGND(ON) vs. Iout .................................................................. 20

Figure 17.

Logic input high level voltage ......................................................... 20

Figure 18.

Logic input low level voltage .......................................................... 20

Figure 19.

High level logic input current.......................................................... 20

Figure 20.

Low level logic input current .......................................................... 21

Figure 21.

Logic input hysteresis voltage......................................................... 21

Figure 22.

Undervoltage shutdown ............................................................. 21

Figure 23.

On-state resistance vs. Tcase ......................................................... 21

Figure 24.

On-state resistance vs. VCC ......................................................... 21

Figure 25.

Turn-on voltage slope .............................................................. 21

Figure 26.

Turn-off voltage slope .............................................................. 22

Figure 27.

Won vs. Tcase ................................................................... 22

Figure 28.

Woff vs. Tcase ................................................................... 22

Figure 29.

ILIMH vs. Tcase ................................................................... 22

Figure 30.

Turn-off output voltage clamp ......................................................... 22

Figure 31.

OFF-state open-load voltage detection threshold ........................................... 22

Figure 32.

Vs clamp vs. Tcase ................................................................ 23

Figure 33.

Vsenseh vs. Tcase ................................................................. 23

Figure 34.

Application diagram................................................................ 25

Figure 35.

Simplified internal structure .......................................................... 25

Figure 36.

MultiSense and diagnostic – block diagram ............................................... 27

Figure 37.

MultiSense block diagram ........................................................... 28

Figure 38.

Analog HSD – open-load detection in off-state ............................................. 29

Figure 39.

Open-load / short to VCC condition ..................................................... 30

Figure 40.

GND voltage shift ................................................................. 31

Figure 41.

Maximum turn off current versus inductance............................................... 32

Figure 42.

PowerSSO-36 PC board ............................................................ 33

Figure 43.

Rthj-amb vs PCB copper area in open box free air conditions .................................... 34

Figure 44.

Power SSO-36 thermal impedance junction ambient single pulse ................................ 35

Figure 45.

Thermal fitting model ............................................................... 35

Figure 46.

PowerSSO-36 package outline ........................................................ 37

Figure 47.

PowerSSO-36 reel 13" ............................................................. 39

Figure 48.

PowerSSO-36 carrier tape ........................................................... 40

Figure 49.

PowerSSO-36 schematic drawing of leader and trailer tape .................................... 41

Figure 50.

PowerSSO-36 marking information ..................................................... 41

VN7000AY

List of figures

DS11412 - Rev 7

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