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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STR710FZ1T6 датащи(PDF) 27 Page - STMicroelectronics |
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STR710FZ1T6 датащи(HTML) 27 Page - STMicroelectronics |
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27 / 74 page  STR71xF Introduction 27/74 1. The Reset configuration of the I/O Ports is IPUPD (input pull-up/pull down). Refer to Table 7 on page 28. The Port bit configuration at reset is PC0=1, PC1=1, PC2=0. The port data register bit (PD) value depends on the pu/pd column which specifies whether the pull-up or pull-down is enabled at reset 2. V33IO-PLL and V33 are internally connected. VSSIO-PLL and VSS are internally connected. 1.6 External Connections Figure 5. Recommended External Connection of V18 and V18BKP pins 63 C4 P0.8/U0.RX/U 0.TX I/O pd CT X4mA T Port 0.8 UART0: Receive Data input UART0: Transmit data output. Note: This pin may be used for single wire UART (half duplex) if programmed as Alternate Function Output. The pin will be tri-stated except when UART transmission is in progress 64 A2 P0.9/U0.TX/B OOT.0 I/O pd CT 4mA X X Port 0.9 Select Boot Configuration input UART0: Transmit data output Table 6. STR711/STR712/STR715 Pin Description Pin n° Pin Name Input Output Main function (after reset) Alternate function LQFP144 LQFP64 58 57 27 129 128 33 nF 59 10 µF 10 µF 33 nF 54 55 1µF 25 26 1µF 28 58 V18BKP V18 V18 V18 V18 V18BKP |
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