LTC6905-XXX Series

5

6905xf

BLOCK DIAGRA

–

+

–

+

+

–

1

3

GAIN = 1

GND

MASTER OSCILLATOR

PROGRAMMABLE

DIVIDER

(N = 1, 2 OR 4)

THREE-STATE

INPUT DETECT

GND

15µA

6905x BD

15µA

OUT

OE

DIVIDER

SELECT

5

DIV

4

2

N

PI FU CTIO S

must be kept free from noise and ripple. It should be

bypassed directly to the GND (Pin 2) with a 0.1µF capacitor

or higher.

GND (Pin 2): Ground. Should be tied to a ground plane for

best performance.

OE (Pin 3): Output Enable. Pull to V+ or leave floating to

enable the output driver (Pin 5). Pull low to disable the

output. The output is disabled asynchronously. Pulling OE

pin low will immediately disable the output. Pulling the OE

pin high will bring the output high on the next low to high

transition of the clock. This eliminates pulse slivers.

DIV (Pin 4): Divider-Setting Input. This three-state input

selects among three divider settings. Pin 4 should be tied

ing Pin 4 divides the master oscillator by 2. Pin 4 should

be tied to GND for the÷4setting,thelowestfrequencyrange.

To detect a floating DIV pin, the LTC6905 attempts to pull

the pin toward midsupply. This is realized with two internal

tied to ground and Pin 4. Therefore, driving the DIV pin high

requires sourcing approximately 15µA. Likewise, driving

DIV low requires sinking 15µA. When Pin 4 is floated, it

should be bypassed by a 1nF capacitor to ground or it should

be surrounded by a ground shield to prevent excessive cou-

pling from other PCB traces.

OUT (Pin 5): Oscillator Output. This pin can drive 5kΩ

and/or 5pF loads. For heavier loads, refer to the Applica-

tions Information section.

Table 1. LTC6905-XXX Frequency Settings

DIV SETTING

LTC6905-133

LTC6905-100

LTC6905-96

LTC6905-80

V+

133.33MHz

100MHz

96MHz

80MHz

OPEN

66.66MHz

50MHz

48MHz

40MHz

GND

33.33MHz

25MHz

24MHz

20MHz