Philips Semiconductors

Product specification

74F651A/74F652A

Transceivers/registers

74F651A Octal transceiver/register, inverting (3-State)

74F652A Octal transceiver/register, non-inverting (3-State)

2

1999 Jun 23

853–1126 21852

FEATURES

and low states)

74F652A

DESCRIPTION

The 74F651A and 74F652A transceivers/registers consist of bus

transceiver circuits with 3–State outputs, D–type flip–flops, and

control circuitry arranged for multiplexed transmission of data

directly from the input bus or the internal registers. Data on the A or

B bus will be clocked into the registers as the appropriate clock pin

goes high. Output enable (OEAB, OEBA) and select (SAB, SBA)

pins are provided for bus management.

TYPE

TYPICAL SUPPLY CURRENT( TOTAL)

74F651/74F652

110MHz

140mA

74F651A/74F652A

175MHz

110mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

INDUSTRIAL RANGE

PKG DWG #

DESCRIPTION

PKG DWG #

24–pin plastic slim DIP (300mil)

N74F651AN, N74F652AN

I74F652AN

SOT222-1

24–pin plastic SOL

N74F651AD, N74F652AD

I74F652AD

SOT137-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

A0 – A7, B0 – B7

A, B inputs

3.5/0.116

70

µA/70µA

CPAB, CPBA

A–to–B, B–to–A clock inputs

1.0/0.033

20

µA/20µA

SAB, SBA

A–to–B, B–to–A select inputs

1.0/0.033

20

µA/20µA

OEAB, OEBA

A–to–B, B–to–A output enable inputs

1.0/0.033

20

µA/20µA

A0 – A7, B0 – B7

A, B outputs for N74F651, N74F652

750/106.7

15mA/64mA

A0 – A7, B0 – B7

A, B outputs for N74F651A, N74F652A

750/80

15mA/48mA

A0 – A7, B0 – B7

A, B outputs for I74F652A

750/60

15mA/36mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.