Philips Semiconductors

Product specification

74F552

Octal registered transceiver with parity and flags (3-State)

2

1991 Jan 02

853–1098 01347

FEATURES

DESCRIPTION

The 74F522 Octal Registered Transceiver contains two 8-bit

registers for temporary storage of data flowing in either direction.

Each register has its own clock (CPR, CPS) and Clock Enable

(CER, CES) inputs, as well as a flag flip-flop that is set automatically

as the register is loaded. The flag output will be reset when the

Output Enable returns to High after reading the output port. Each

register has a separate Output Enable (OEAS, OEBR) for its 3-State

buffer. The separate Clocks, Flags and Enables provide

considerable flexibility as I/O ports for demand-response data

transfer. When data is transferred from the A port to the B port, a

parity bit is generated. On the other hand, when data is transferred

from the B port to the A port, the parity of input data on B0–B7 is

checked.

TYPE

TYPICAL SUPPLY

CURRENT

(TOTAL)

74F552

85MHz

120mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

28-Pin Plastic DIP

(600mil)

N74F552N

SOT117-2

28-Pin Plastic SOL

N74F552D

SOT136-1

LOGIC SYMBOL

26

27

28

GND = Pin 22

18

17

16

15

14

13

12

21

20

SF01041

CPS

B0

B1

B4

B5

B6

B7

CES

A0

A1

A4

A5

A6

A7

B2

B3

A3

A2

12

3

4

25

11

6

7

CER

CPR

19

5

OEBR

OEAS

24

9

FR

23

10

FS

PARITY

ERROR

PIN CONFIGURATION

SF01039

1

2

3

4

5

6

7

8

9

10

11

12

17

18

19

20

21

22

23

24

25

26

27

28

B4

B5

B6

OEBR

CPR

CER

ERROR

FS

A7

B3

B2

B1

B0

FR

PARITY

GND

CPS

CES

OEAS

A0

A1

A6

13

16 A2

A5

14

15 A3

A4

B7

LOGIC SYMBOL (IEEE/IEC)

25

26

27

28

1

2

3

4

18

17

16

15

14

13

12

11

1C2

EN1’

EN6

6C4

EN3

EN6

SF01040

1,2,6

3,4,6

20

6

7

5

21

19

5,6

5,6

6

6,7

5

23

9

10

14

XCVR

Z7