VSOP383..

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Vishay Semiconductors

Rev. 1.4, 30-Jul-2021

4

Document Number: 82748

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 6 - Sensitivity vs. Temperature

Fig. 7 - Maximum Envelope Duty Cycle

PACKAGE DIMENSIONS in millimeters

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

- 30

- 10

10

30

50

70

90

T

amb - Ambient Temperature (°C)

21542

N - Burstlength (Carrier Cycles)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

020

40

60

80

100

VSOP383..

I

IN = 5 nA

Proposed hole layout

from component side

(for reference only)

technical drawings

according to DIN

specifications

Not indicated tolerances ± 0.1

Drawing-No.: 6.550-5314.01-4

Issue: 3; 07.12.15

2

0.5 typ. (6 x)

(8 x)

0.25 ± 0.05

1.6 ± 0.15

10:1

0.35 (8 x)

0.5 (6 x)

1. Coplanarity (0.1 mm)

applies to the exposed

pad as well as the

exposed terminals.

2. Package dimension does not

include mold flash, protrusions,

burrs or metal smearing.

1

Pinning:

1. n.c.

2. V

S

3. Out

4. n.c.

5. n.c.

6. GND

7. IN

8. GND

3338

YWW

For example 38 kHz

Marking area

PIN 1 indicator

Chamfered corner

PIN 1 indicator

Exposed pad

0.1

4

85