Philips Semiconductors

Product specification

74F398*,74F399

Registers

74F398 Quad 2-Port Register with True and Complementary Outputs

74F399 Quad 2-Port Register

2

1999 Jan 08

853–0028 20616

* Discontinued part. Please see the Discontinued Products List..

FEATURES

DESCRIPTION

The 74F398 and 74F399 are the logical equivalent of a quad 2-input

multiplexer feeding into four edge-triggered flip-flops. A common

Select input determines which of two 4-bit words is accepted. The

selected data enters the flip-flops on the rising edge of the clock.

The 74F399 is the 16-pin version of the 74F398, with only the true

(Qn) outputs of the flip-flops available.

The 74F398 and 74F399 are high speed quad 2-port registers. They

select 4 bits of data from either of two sources (Ports) under control

of a common select input (S). The selected data is transferred to a

4-bit output register synchronous with the Low-to-High transition of

the Clock input (CP). The 4-bit D-type output register is fully

edge-triggered. The Data inputs (I0n, I1n) and Select input (S) must

be stable only a setup time prior to and hold time after the

Low-to-High transition of the Clock input for predictable operation.

The 74F398 has both Q and Q outputs.

TYPE

TYPICAL SUPPLY CURRENT

(TOTAL)

74F398

120MHz

25mA

74F399

120MHz

22mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F399N

SOT38-4

16-pin plastic SO

N74F399D

SOT109-1

PIN CONFIGURATION – 74F398

20

19

18

17

16

15

14

7

6

5

4

3

2

1

I0b

I1d

I1c

I0c

I0d

Qd

Qd

S

Qa

I1b

Qa

I0a

I1a

SF00947

13

8

QbQc

12

9

Qb

Qc

11

10

GND

CP

PIN CONFIGURATION – 74F399

16

15

14

13

12

11

6

5

4

3

2

1

I0b

I1d

I1c

I0c

I0d

Qd

S

Qa

I1b

I0a

I1a

SF00951

10

7

Qb

Qc

9

8

GND

CP

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

I0a, I0b, I0c, I0d

Data inputs from source 0

1.0/1.0

20

µA/0.6mA

I1a, I1b, I1c, I1d

Data inputs from source 1

1.0/1.0

20

µA/0.6mA

S

Common Select input

1.0/1.0

20

µA/0.6mA

CP

Clock input (active rising edge)

1.0/1.0

20

µA/0.6mA

Qa, Qb, Qc, Qd

Register true outputs

50/33

1.0mA/20mA

Qa, Qb, Qc, Qd

Register complementary outputs (74F398)

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.