Philips Semiconductors

Product specification

74F378

Hex D flip-flop with enable

2

1989 Oct 05

853–0067 97804

FEATURES

DESCRIPTION

The 74F378 has six edge-triggered D-type flip-flops with individual

D inputs and Q outputs. The common buffered Clock (CP) input

loads all flip-flops simultaneously when the Enable (E) input is Low.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition is transformed to

the corresponding flop-flop’s Q output. The E input must be stable

one setup time prior to the Low-to-High clock transition for

predictable operation.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

VCC

E

Q0

D0

D1

Q1

D2

Q2

GND

Q5

D5

D4

Q4

D3

Q3

CP

SF00927

TYPE

TYPICAL SUPPLY

CURRENT (TOTAL)

74F378

100MHz

35mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL

RANGE

PKG DWG #

16–pin plastic DIP

N74F378N

SOT38-4

16–pin plastic SO

N74F378D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D5

Data inputs

1.0/1.0

20

µA/0.6mA

CP

Clock pulse input (active rising edge)

1.0/1.0

20

µA/0.6mA

E

Enable input (active low)

1.0/1.0

20

µA/0.6mA

Q0 – Q5

Data outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.