Philips Semiconductors

Product specification

74F373/74F374

Latch/flip-flop

74F373 Octal transparent latch (3-State)

74F374 Octal D-type flip-flop (3-State)

2

December 5, 1994

853-0369 14383

FEATURES

DESCRIPTION

The 74F373 is an octal transparent latch coupled to eight 3-State

output devices. The two sections of the device are controlled

independently by enable (E) and output enable (OE) control gates.

The data on the D inputs is transferred to the latch outputs when the

enable (E) input is high. The latch remains transparent to the data

input while E is high, and stores the data that is present one setup

time before the high-to-low enable transition.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors.

The active low output enable (OE) controls all eight 3-State buffers

independent of the latch operation. When OE is low, latched or

transparent data appears at the output.

When OE is high, the outputs are in high impedance “off” state,

which means they will neither drive nor load the bus.

The 74F374 is an 8-bit edge triggered register coupled to eight

3-State output buffers. The two sections of the device are controlled

independently by clock (CP) and output enable (OE) control gates.

The register is fully edge triggered. The state of the D input, one

setup time before the low-to-high clock transition is transferred to the

corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded

3-State buses, MOS memories, or MOS microprocessors.

The active low output enable (OE) controls all eight 3-State buffers

independent of the register operation. When OE is low, the data in

the register appears at the outputs. When OE is high, the outputs

are in high impedance “off” state, which means they will neither drive

nor load the bus.

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL SUPPLY

CURRENT

(TOTAL)

74F373

4.5ns

35mA

TYPE

TYPICAL SUPPLY

CURRENT

(TOTAL)

74F374

165MHz

55mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

20-pin plastic DIP

N74F373N, N74F374N

SOT146-1

20-pin plastic SOL

N74F373D, N74F374D

SOT163-1

20-pin plastic SSOP type II

N74F373DB, N74374DB

SOT399-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 - D7

Data inputs

1.0/1.0

20

µA/0.6mA

E (74F373)

Enable input (active high)

1.0/1.0

20

µA/0.6mA

OE

Output enable inputs (active low)

1.0/1.0

20

µA/0.6mA

CP (74F374)

Clock pulse input (active rising edge)

1.0/1.0

20

µA/0.6mA

Q0 - Q7

3-State outputs

150/40

3.0mA/24mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.