Philips Semiconductors

Product specification

74F32

Quad 2-input OR gate

2

October 4, 1990

853 0333 00624

FEATURE

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F32

4.1ns

8.2mA

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

D2b

D2a

Q2

Q3

D3b

D3a

D0a

D0b

Q1

Q0

D1a

D1b

SF00038

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

INDUSTRIAL RANGE

PKG DWG #

14-pin plastic DIP

N74F32N

I74F32N

SOT27-1

14-pin plastic SO

N74F32D

I74F32D

SOT108–1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

Dna, Dnb

Data inputs

1.0/1.0

20

µA/0.6mA

Qn

Data output

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.

LOGIC DIAGRAM

D0a

D0b

D1a

D1b

D2a

Q0

D2b

D3a

D3b

Q1

Q2

Q3

GND = Pin 7

3

6

8

11

1

2

4

5

9

10

12

13

SF00039

FUNCTION TABLE

INPUTS

OUTPUT

Dna

Dnb

Qn

L

L

L

L

H

H

H

L

H

H

H

H

NOTES:

1

H = High voltage level

2

L = Low voltage level

LOGIC SYMBOL

D0a D0b D1a

D2a D2b D3a D3b

D1b

Q0 Q1 Q2 Q3

36

8

11

12

4

5

9

10 12 13

GND = Pin 7

SF00040

IEC/IEEE SYMBOL

1

2

4

5

9

10

12

13

3

6

8

11

SF00041

1