Philips Semiconductors

Product specification

74F298

Quad 2-input multiplexer with storage

2

1989 Aug 14

853–0061 97377

FEATURES

MSI functions (74F157 and 74F175)

DESCRIPTION

The 74F298 is a high speed Quad 2-Input Multiplexer with storage.

It selects 4 bits of data from two sources (ports) under the control of

a common Select input (S). The selected data is transferred to the

4-bit output register synchronous with the High-to-Low transition of

the clock (CP). The 4-bit register is fully edge triggered. The data

inputs (I0 and I1) and Select input (S) must be stable only one setup

time prior to the High-to-Low transition of the clock for predictable

operation.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

I0d

Qd

CP

S

Qc

Qa

Qb

I1b

I1a

I1d

I0a

I0b

I1c

9

8

GND

I0c

SF00859

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F298

115MHz

30mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F298N

SOT38-4

16-pin plastic SO

N74F298D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

I0a, I0b, I0c, I0d

Data inputs

1.0/1.0

20

µA/0.6mA

I1a, I1b, I1c, I1d

Data inputs

1.0/1.0

20

µA/0.6mA

S

Select input

1.0/1.0

20

µA/0.6mA

CP

Clock input (active falling edge)

1.0/1.0

20

µA/0.6mA

Qa, Qb, Qc, Qd

Data outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

GND = Pin 8

SF00860

10

11

S

CP

3241

957

I0a

I1a

I0b

I1b

I0c

I1c

I0d

Qa

Qb

Qc

Qd

15

14

13

12

6

I1d

LOGIC SYMBOL (IEEE/IEC)

SF00861

3

2, 1D

11

C1

10

M2

2

15

2, 1D

4

1

14

9

5

13

7

6

12