Philips Semiconductors

Product specification

74F2952, 74F2953

Transceivers

74F2952

Registered transceiver, non-inverting (3-State)

74F2953

Registered transceiver, inverting (3-State)

2

1989 Sep 22

853–1097 97708

FEATURES

directions between two bidirectional buses

each register

DESCRIPTION

The 74F2952 and 74F2953 are 8-bit registered transceivers. Two

8-bit back-to-back registers store data flowing in both directions

between two bi-directional buses. Data applied to the inputs is

entered and stored on the rising edge of the Clock (CPXX) provided

that the Clock Enable (CEXX) is Low. The data is then present at

the 3-State output buffers, but is only accessible when the Output

Enable (OEXX) is Low. Data flow from ‘A’ inputs to ‘B’ outputs is the

same as for ‘B’ inputs to ‘A’ outputs.

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F2952

160MHz

105mA

74F2953

160MHz

105mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PACKAGE

DRAWING

NUMBER

24-pin Plastic Slim DIP (300mil)

N74F2952N, N74F2953N

SOT222-1

N74F2952D, N74F2953D

SOT137-1

28-pin Plastic Leaded Chip Carrier

N74F2952A, N74F2953A

SOT261-2

NOTE:

1. Thermal mounting techniques are recommended. See

SMD Process Applications for a discussion of thermal consideration for surface

mounted devices.

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 – A7

Port A, 3-State inputs

3.5/1.0

70

µA/0.6mA

B0 – B7

Port B, 3-State inputs

3.5/1.0

70

µA/0.6mA

CPAB, CPBA

Clock inputs

1.0/1.0

20

µA/0.6mA

CEAB, CEBA

Clock Enable inputs

1.0/1.0

20

µA/0.6mA

OEAB, OEBA

Output Enable inputs

1.0/1.0

20

µA/0.6mA

A0 – A7

Port A, 3-State outputs

150/40

3.0mA/24mA

B0 – B7

Port B, 3-State outputs

750/106.7

15mA/64mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.